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Routing congestion in VLSI circuits : estimation and optimization / Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar

  • Linear

  • MARC

  •  
    TK7874.75
    .S39 2007
     
    817543 (Shelf),BOK
    Saxena, Prashant

         Routing congestion in VLSI circuits : estimation and optimization. - New York , 2007.

         xiv, 248 p. : ill. ; 24 cm Series on integrated circuits and systems.

         ISBN 9780387300375 (cased)
         .-ISBN 0387300376 (cased).
         
         1. Integrated circuits - Very large scale integration 2. Routing (Computer network management).I. Shelar, Rupesh S. II. Sapatnekar, Sachin S.,1967- III. Title IV. Series
         Library : UiTM Shah Alam
    Accn No.Item StatusAdd IdLocationSMDItem Category
    817543ShelfPERPUSTAKAAN KEJURUTERAAN TAR(P3)BOOKRAK TERBUKA (OPEN SHELVES)

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