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System-on-chip test architectures : nanometer design for testability / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba

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  • MARC

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    TK7895.E42
    S978 2008
     
    815138 (Shelf),BOK
    System-on-chip test architectures : nanometer design for testability. - Amsterdam. - Boston , 2008.

         xxxvi, 856 p. : ill. ; 25 cm The Morgan Kaufmann series in systems on silicon.

         ISBN 9780123739735 (hardcover : alk. paper)
         .-ISBN 012373973X (hardcover : alk. paper).
         
         1. Systems on a chip - Testing 2. Integrated circuits - Very large scale integration - Testing 3. Integrated circuits - Very large scale integration - Design.I. Wang, Laung-Terng II. Stroud, Charles E. III. Touba, Nur A. IV. Title V. Series
         Library : UiTM Shah Alam
    Accn No.Item StatusAdd IdLocationSMDItem Category
    815138ShelfPERPUSTAKAAN KEJURUTERAAN TAR(P3)BOOKRAK TERBUKA (OPEN SHELVES)

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