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Verification methodology manual for SystemVerilog / by Janick Bergeron ... [et al.]

  • Linear

  • MARC

  •  
    TK7885.7
    .V44 2006
     
    650877 (Shelf),BOK
    Verification methodology manual for SystemVerilog. - New York , 2006.

         xvii, 503 p. : ill. ; 24 cm.

         ISBN 0387255389
         .-ISBN 9780387255385 (alk. paper)
         .-ISBN 0387255567 (e-book).
         
         1. Verilog (Computer hardware description language) - Verification 2. Integrated circuits - Verification.I. Bergeron, Janick II. Title
         Library : UiTM Shah Alam
    Accn No.Item StatusAdd IdLocationSMDItem Category
    650877ShelfPERPUSTAKAAN KEJURUTERAAN TAR(P3)BOOKRAK TERBUKA (OPEN SHELVES)
    683639ShelfPERPUSTAKAAN KEJURUTERAAN TAR(P3)BOOKRAK TERBUKA (OPEN SHELVES)

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