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Logic synthesis and verification algorithms / Gary D. Hachtel, Fabio Somenzi

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  • MARC

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    TK7874.75
    .H33 2002
     
    652991 (Shelf),BOK
    Hachtel, Gary D

         Logic synthesis and verification algorithms. - New York , 2006.

         xxxii, 597 p. : ill ; 24 cm.

         ISBN 0387310053
         .-ISBN 0306475928
         .-ISBN 0387310045 (softcover : alk. paper).
         
         1. Computer-aided design 2. Logic design - Data processing 3. Integrated circuits - Very large scale integration - Design and construction - Data processing 4. Integrated circuits - Verification.I. Somenzi, Fabio II. Title
         Library : UiTM Shah Alam
    Accn No.Item StatusAdd IdLocationSMDItem Category
    652991ShelfPERPUSTAKAAN KEJURUTERAAN TAR(P3)BOOKRAK TERBUKA (OPEN SHELVES)

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