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Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi

  • Linear

  • MARC

  •  
    TK7874.75
    .H33 1996
     
    484040 (Shelf),BOK
    Hachtel, Gary D.

         Logic synthesis and verification algorithms. - Boston , 1996.

         xxiii, 564 p. : ill. ; 24 cm.

         ISBN 0792397460.
         
         1. Login design - Data processing 2. Integrated circuits - Verification 3. Integrated circuits - Very large scale integration - Design - Data processing.I. Somenzi, Fabio II. Title
         Library : UiTM Shah Alam
    Accn No.Item StatusAdd IdLocationSMDItem Category
    484040ShelfPERPUSTAKAAN KEJURUTERAAN TAR(P3)BOOKret

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